The present disclosure relates to the field of display technology, and particularly, to an array substrate and a manufacturing method for the same, and a display device.
FIG. 1 is a schematic equivalent circuit diagram of an array substrate of a display panel in the prior art. In the structure of a conventional gate line shielded Advanced Super Dimension Switch (ADS) display panel, a shield electrode 1 for shielding a gate line 3 is connected to a common electrode 2 in the pixel region. In the schematic equivalent circuit diagram as FIG. 1, the shield electrode 1 and the common electrode 2 are equivalent to directly connected wires. Since the operation principle of the shield electrode 1 is to vary synchronously with the signal on the gate line 3 to prevent the electric field generated by the change of a current on the gate lines 3 from affecting other circuit elements, the shield electrode 1 is affected by the signal on the gate line 3. When the common electrode 2 is directly connected to the shield electrode 1, the shield electrode 1 further affects the common electrode 2 in the pixel region.
FIG. 2 is a schematic diagram of a distribution of the common electrode delay difference of a display panel in the prior art. As shown in FIG. 2, the common electrodes 2 affected by the shield electrodes 1 generate common electrode delays, which are different at different positions of the panel. In the display panel, the difference of the delays of the common electrodes 2 produces uneven brightness (MURA defect), so that a visible display defect occurs on the surface of a pixel matrix composed of a plurality of pixel regions when the display panel operates.